Prof. Kim`s R.P.

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  • 39 J. B. Choi, S. W. Kim, K. S. Roh, S. H. Seo, K. Y. Kim, C. H. Lee, S. Y. Lee, J. U. Lee, G. C. Kang, H. T. Kim, D. H. Kim, K. S. Min, D. J. Kim, and D. M. Kim "Optical Trap-Assisted Tunneling Current Method for Extracting thr Interface-State Density in the Gate-to-Drain Overlapped Region of MOSFETs" The 13th Korean Conference on Semiconductors, vol. 2, pp. 817-818, 2006-02 PDF
  • 38 J. B. Choi, S. W. Kim, K. S. Roh, S. H. Seo, K. Y. Kim, C. H. Lee, S. Y. Lee, J. U. Lee, G. C. Kang, H. T. Kim, D. H. Kim, K. S. Min, D. J. Kim, and D. M. Kim "Optical Trap-Assisted Tunneling Current Method for Extracting thr Interface-State Density in the Gate-to-Drain Overlapped Region of MOSFETs" The 13th Korean Conference on Semiconductors, vol. 2, pp. 817-818, 2006-02
  • 37 강경민, 최훈대, 강경필, 곽동곤, 권오삼, 임진혁, 김대환, 송호준, 김대정, 김동명, 민경식 "Low-Latency and High-Bandwidth Multi-Channel SDRAM Controller Using Predictive Reordering Scheme for Multimedia SoC" The 13th Korean Conference on Semiconductors, vol. 2, pp. 925-926, 2006-02
  • 36 강경민, 최훈대, 강경필, 곽동곤, 권오삼, 임진혁, 김대환, 송호준, 김대정, 김동명, 민경식 "FPGA Implementation of Multi-Channel SDRAM Controller" The 13th Korean Conference on Semiconductors, vol. 1, pp. 579-582, 2006-02
  • 35 곽동곤, 최훈대, 강경민, 권오삼, 김대환, 송호준, 김대정, 김동명, 민경식 "Row-By-Row Activated SRAM with Process-VDD-Temperature (PVT) Fluctuation Adaptive Source-Line Biasing Circuit for Low-Leakage Sub-70-nm LSI’s" The 13th Korean Conference on Semiconductors, vol. 1, pp. 199-200, 2006-02
  • 34 강경필, 최훈대, 강경민, 곽동곤, 권오삼, 김대환, 송호준, 김대정, 김동명, 민경식 "Charge-Recycling Dynamic VTH Scaling (DVTS) Circuit for Leakage-Dominant VLSI’s" The 13th Korean Conference on Semiconductors, vol. 1, pp. 173-174, 2006-02
  • 33 K. R. Kim, H. H. Kim, J.-I. Huh, D. H. Kim, K.-W. Song, J. D. Lee, and B.-G. Park "Field Induced Band-to-Band Tunneling Effect Transistor - FIBTET with Negative-Differential Transconductance and Negative-Differential Conductance Characteristics" IEEE 2004 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 11-12, 2004-06
  • 32 J. I. Huh, D. H. Kim, K. R. Kim, H. H. Kim, K.-W. Song, J. D Lee, and B.-G. Park "Coupled Parallel Quantum Dots in Silicon Single-Electron Transistors by the Three-Dimensional Field Effects" IEEE 2004 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 83-84, 2004-06
  • 31 B.-G. Park, D. H. Kim, K. R. Kim, K.-W. Song, and J. D. Lee "Single-Electron Transistors Fabricated with Sidewall Spacer Patterning" 6th International Conference on New Phenomena in Mesoscopic Structures 6 Surfaces and Interfaces in Mesoscopic Devices 4, pp.108-109, Hawaii, USA, 2003-11 PDF
  • 30 K.-W. Song, G. Baek, S.-H. Lee, D. H. Kim, K. R. Kim, D.-S. Woo, J. S. Sim, J. D. Lee, and B.-G. Park "Realistic Single-Electron Transistor Modeling and Novel CMOS/SET Hybrid Circuits" 2003 Thrid IEEE Conference on Nanotechnology(IEEE-NANO 2003), pp.119-121, San Francisco, California, USA, 2003-08 PDF
  • 29 K. R. Kim, D. H. Kim, K.-W. Song, S.-H. Lee, J. Kyung, J. D. Lee, and B.-G. Park "Observation of Single-Electron Charging Effects Based on Band-to-band Tunneling in a MOS-based Single-Electron Transistor-"MOSET"" IEEE 2003 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 72-73, 2003-06
  • 28 K.-W. Song, S. H. Lee, D. H. Kim, K. R. Kim, J. Kyung, G. Baek, C.-A. Lee, J. D. Lee, and B.-G. Park "Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic" 33rd International Symposium on Multiple-Valued Logic, Tokyo, Japan, pp.267-272, 2003-05 PDF
  • 27 S.-H. Lee, K.-W. Song, D. H. Kim, K. R. Kim, J. D. Lee, B.-G. Park, Y.-J. Gu, G.-Y. Yang, Y.-K. Park, and J.-T. Kong "A SPICE Model of Realistic Single-Electron Transistors and its Application to Multiple-Valued Logic" The 10th Korean Conference on Semiconductors, Seoul, Korea, pp. 109-110, 2003-02 PDF
  • 26 D. H. Kim, S.-K Sung, K. R. Kim, J. D. Lee, and B.-G. Park "Single-Electron Transisters Based on Gate-Induced Si Island for Single-Electron Logic Application" IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 57-58, 2002-06 PDF
  • 25 K. R. Kim, D. H. Kim, J. D. Lee, and B.-G. Park "Room Temperature Negative Differential Conductance Characteristics in 30-nm Square Channel Silicon-On-Insulator n-MOSFETs" IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 9-10, 2002-06
  • 24 S. H. Lee, D. H. Kim, K.-R. Kim, J. D. Lee, and B.-G. Park "A Practival SPICE Model Based on Realistic Single-Electron Transistor" IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 77-78, 2002-06
  • 23 J. S. Sim, S. K. Sung, D.-H. Chae, D. H. Kim, J. D. Lee, and B.-G. Park "Programming Characteristics of Single Quantum Dot and Nanocrystal Memories" IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 65-66, 2002-06
  • 22 D. H. Kim, S.-K Sung, K. R. Kim, J. D. Lee, and B.-G. Park "Single-Electron Transistors with Sidewall Depletion Gates on an SOI Nanowire and Their Application to Single-Electron Inverter" The 9th Korean Conference on Semiconductors, Chunan, Korea, pp. 91-92, 2002-02
  • 21 D. H. Kim, S.-K. Sung, K. R. Kim, B. H. Choi, S. W. Hwang, D. Ahn, J. D. Lee, and B.-G. Park "Si Single-Electron Transistors with Sidewall Depletion Gates and their Application to Dynamic Single-Electron Transistor Logic" International Electron Devices Meeting, Washington DC, U.S.A., pp. 151-154, 2001-12 PDF
  • 20 B. H. Choi, S. H. Son, K. H. Cho, S. W. Hwang, D. Ahn, D. H. Kim, B. G. Park "Direct observation of excited states in double quantum dot silicon single electron transistor" Fifth International Symposium on New Phenomena in Mesoscopic Structures, p. 36, Big Island, Hawaii, U.S.A., 2001-11 PDF